K30P64M72SF1 Datasheet, PDF (26/68 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
Min.
f_{loc_high} Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
f_{ints_t}
FLL
f_{fll_ref} FLL reference frequency range
31.25
f_dco
DCO output
Low range (DRS=00)
20
frequency range
640 × f_{fll_ref}
Mid range (DRS=01)
40
1280 × f_{fll_ref}
Mid-high range (DRS=10)
60
1920 × f_{fll_ref}
High range (DRS=11)
80
2560 × f_{fll_ref}
f_{dco_t_DMX3} DCO output
2
frequency
Low range (DRS=00)
—
732 × f_{fll_ref}
Mid range (DRS=01)
—
1464 × f_{fll_ref}
Mid-high range (DRS=10)
—
2197 × f_{fll_ref}
High range (DRS=11)
—
2929 × f_{fll_ref}
J_{cyc_fll} FLL period jitter
—
• f_VCO = 48 MHz
• f_VCO = 98 MHz
—
t_{fll_acquire} FLL target frequency acquisition time
—
PLL
f_vco
VCO operating frequency
48.0
I_pll
PLL operating current
• PLL @ 96 MHz (f_{osc_hi_1} = 8 MHz, f_{pll_ref} =
—
2 MHz, VDIV multiplier = 48)
I_pll
PLL operating current
• PLL @ 48 MHz (f_{osc_hi_1} = 8 MHz, f_{pll_ref} =
—
2 MHz, VDIV multiplier = 24)
f_{pll_ref} PLL reference frequency range
2.0
J_{cyc_pll} PLL period jitter (RMS)
• f_vco = 48 MHz
—
• f_vco = 100 MHz
—
Typ.
—
—
20.97
41.94
62.91
83.89
23.99
47.97
71.99
95.98
180
150
—
—
1060
600
—
120
50
Max.
—
39.0625
25
50
75
100
—
—
—
—
—
—
1
100
—
—
4.0
—
—
Table continues on the next page...
Unit
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ms
MHz
µA
µA
MHz
ps
ps
Notes
2, 3
4, 5
6
7
7
8
K30 Sub-Family Data Sheet, Rev. 2, 4/2012.
26
Freescale Semiconductor, Inc.