K30P64M72SF1 Datasheet, PDF (38/68 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Peripheral operating requirements and behaviors
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The R_AS/
C_AS time constant should be kept to <1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/
files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
Z_AS
R_AS
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
leakage
due to
input
protection
Z_ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
R_ADIN
ADC SAR
ENGINE
V_ADIN
V_AS
C_AS
INPUT PIN
INPUT PIN
INPUT PIN
R_ADIN
R_ADIN
R_ADIN
C_ADIN
Figure 12. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 24. 16-bit ADC characteristics (V_REFH = V_DDA, V_REFL = V_SSA)
Symbol Description
I_{DDA_ADC} Supply current
f_ADACK
ADC
asynchronous
clock source
Conditions¹
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
Min.
0.215
1.2
3.0
2.4
4.4
Typ.²
—
2.4
4.0
5.2
6.2
Max.
1.7
3.9
7.3
6.1
9.5
Unit
mA
MHz
MHz
MHz
MHz
TUE
Sample Time
See Reference Manual chapter for sample times
Total unadjusted
error
• 12 bit modes
• <12 bit modes
—
±4
—
±1.4
±6.8
±2.1
LSB⁴
DNL
Differential non-
linearity
• 12 bit modes
—
±0.7
• <12 bit modes
—
±0.2
Table continues on the next page...
-1.1 to
+1.9
-0.3 to 0.5
LSB⁴
Notes
3
t_ADACK = 1/
f_ADACK
5
5
K30 Sub-Family Data Sheet, Rev. 2, 4/2012.
38
Freescale Semiconductor, Inc.