K30P64M72SF1 Datasheet, PDF (36/68 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Peripheral operating requirements and behaviors
Table 22. EzPort switching specifications (continued)
Num
EP9
Description
EZP_CS negation to EZP_Q tri-state
Min.
Max.
Unit
—
12
ns
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP3
EP4
EP2
EP9
EP8
EP7
EP5
EP6
Figure 11. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 25 and
Table 26.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
K30 Sub-Family Data Sheet, Rev. 2, 4/2012.
36
Freescale Semiconductor, Inc.