K30P64M72SF1 Datasheet, PDF (19/68 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Symbol
C_{IN_D}
Table 7. Capacitance attributes (continued)
Description
Input capacitance: digital pins
Min.
—
Max.
7
General
Unit
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 8. Device clock specifications
Symbol Description
f_SYS
f_BUS
f_FLASH
f_LPTMR
System and core clock
Bus clock
Flash clock
LPTMR clock
f_SYS
System and core clock
f_BUS
Bus clock
f_FLASH
Flash clock
f_ERCLK
External reference clock
f_{LPTMR_pin} LPTMR clock
f_{LPTMR_ERCLK} LPTMR external reference clock
f_{FlexCAN_ERCLK} FlexCAN external reference clock
f_{I2S_MCLK} I2S master clock
f_{I2S_BCLK}
I2S bit clock
Normal run mode
VLPR mode¹
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
72
50
25
25
4
4
1
16
25
16
8
12.5
4
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I²C signals.
K30 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
19