MC68HC908AB32 Datasheet, PDF (361/392 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Voltage Inhibit (LVI)
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 21-2. LVI I/O Register Summary
21.4.1 Polled LVI Operation
In applications that can operate at V_DD levels below the LVI_TRIPF level,
software can monitor V_DD by polling the LVIOUT bit. In configuration
register 1, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
21.4.2 Forced Reset Operation
In applications that require V_DD to remain above the LVI_TRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when V_DD
falls below the LVI_TRIPF level and remains at or below that level for 9 or
more consecutive CPU cycles. In configuration register 1, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
21.4.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU, V_DD must
remain at or below the LVI_TRIPF level for 9 or more consecutive CPU
cycles. V_DD must be above LVI_TRIPR for only one CPU cycle to bring the
MCU out of reset.
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor
Low-Voltage Inhibit (LVI)
Technical Data
361