MC68HC908AB32 Datasheet, PDF (133/392 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
9.4 Functional Description
The CGM consists of three major sub-modules:
• Crystal oscillator circuit which generates the constant crystal
frequency clock, CGMXCLK.
• Phase-locked loop (PLL) which generates the programmable
VCO frequency clock CGMVCLK.
• Base clock selector circuit; this software-controlled circuit selects
either CGMXCLK divided by two or the VCO clock CGMVCLK
divided by two, as the base clock CGMOUT. The SIM derives the
system clocks from CGMOUT.
Figure 9-1 shows the structure of the CGM.
OSC2
CRYSTAL OSCILLATOR
OSC1
SIMOSCEN
CGMRDV
CGMRCLK
CLOCK
SELECT
÷2
CIRCUIT
BCS
V_DDA CGMXFC
V_SS
VRS[7:4]
CGMXCLK
TO SIM, SCI
A
B _S*
CGMOUT
TO SIM
*When S = 1, CGMOUT = B
USER MODE
PTC3
MONITOR MODE
PHASE
DETECTOR
LOOP
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
PLL ANALOG
LOCK
DETECTOR
BANDWIDTH
CONTROL
INTERRUPT
CONTROL
CGMINT
LOCK
CGMVDV
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor
AUTO ACQ
MUL[7:4]
PLLIE PLLF
FREQUENCY
DIVIDER
CGMVCLK
Figure 9-1. CGM Block Diagram
Clock Generator Module (CGM)
Technical Data
133