MC68HC908AB32 Datasheet, PDF (144/392 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
Addr.
$001C
$001D
$001E
Register Name
Bit 7
Read:
PLL Control Register
(PCTL)
Write:
Reset:
PLLIE
0
PLL Bandwidth Control ^Read:
Register Write:
(PBWC) _Reset:
AUTO
0
PLL Programming ^Read:
Register Write:
(PPG) _Reset:
MUL7
0
6
PLLF
5
PLLON
0
1
LOCK
ACQ
0
0
MUL6 MUL5
1
1
= Unimplemented
4
BCS
0
XLD
0
MUL4
0
3
1
1
0
0
VRS7
0
NOTES:
1. When AUTO = 0, PLLIE is forced to logic zero and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic zero.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 9-4. CGM I/O Register Summary
2
1
1
0
0
VRS6
1
1
1
1
0
0
VRS5
1
Bit 0
1
1
0
0
VRS4
0
9.6.1 PLL Control Register (PCTL)
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Address: $001C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLLIE
PLLON BCS
Write:
Reset: 0
0
1
0
1
1
1
1
= Unimplemented
Figure 9-5. PLL Control Register (PCTL)
Technical Data
144
Clock Generator Module (CGM)
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor