MC68HC908AB32 Datasheet, PDF (156/392 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
whether the PLL is within the lock mode entry tolerance ∆_LOCK.
Therefore, the acquisition time t_ACQ, is an integer multiple of n_ACQ/f_RDV,
and the acquisition to lock time t_AL, is an integer multiple of n_TRK/f_RDV.
Also, since the average frequency over the entire measurement period
must be within the specified tolerance, the total time usually is longer
than t_LOCK as calculated above.
In manual mode, it is usually necessary to wait considerably longer than
t_LOCK before selecting the PLL clock (see 9.4.3 Base Clock Selector
Circuit), because the factors described in 9.10.2 Parametric
Influences On Reaction Time may slow the lock time considerably.
Technical Data
156
Clock Generator Module (CGM)
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor