MC68HC908AB32 Datasheet, PDF (120/392 Pages) Motorola, Inc – HCMOS Microcontroller Unit

System Integration Module (SIM)
FROM RESET
I BBIRTESAEKT?
INTERRUPT?
YES
NO
YES
I-BIT SET?
NO
IRQ
INTERRUPT?
YES
NO
AS MANY INTERRUPTS
AS EXIST ON CHIP
STACK CPU REGISTERS
SET I-BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
YES
INSTRUCTION?
NO
RTI
YES
INSTRUCTION?
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 8-10. Interrupt Processing
8.6.1.1 Hardware Interrupts
Processing of a hardware interrupt begins after completion of the current
instruction. When the instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I-bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
Technical Data
120
System Integration Module (SIM)
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor