MC9S08DN60_08 Datasheet, PDF (338/356 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix B Timer Pulse-Width Modulator (TPMV2)
CPWMS
X
0
1
MSnB:MSnA
XX
00
01
1X
XX
Table B-5. Mode, Edge, and Level Selection
ELSnB:ELSnA
Mode
Configuration
00
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
01
Input capture Capture on rising edge only
10
Capture on falling edge only
11
Capture on rising or falling edge
00
Output
Software compare only
compare
01
Toggle output on compare
10
Clear output on compare
11
Set output on compare
10
Edge-aligned High-true pulses (clear output on compare)
PWM
X1
Low-true pulses (set output on compare)
10
Center-aligned High-true pulses (clear output on compare-up)
PWM
X1
Low-true pulses (set output on compare-up)
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
B.2.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
7
6
5
4
3
2
R
Bit 15
14
13
12
11
10
W
1
0
9
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure B-8. Timer Channel Value Register High (TPMxCnVH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure B-9. Timer Channel Value Register Low (TPMxCnVL)
MC9S08DN60 Series Data Sheet, Rev 3
338
Freescale Semiconductor