MC9S08DN60_08 Datasheet, PDF (272/356 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 15 Timer/PWM Module (S08TPMV3)
Table 15-5. TPMxCnSC Field Descriptions (continued)
Field
4
MSnA
3–2
ELSnB
ELSnA
Description
Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for
input-capture mode or output compare mode. Refer to Table 15-6 for a summary of channel mode and setup
controls.
Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger.
Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA
and shown in Table 15-6, these bits select the polarity of the input edge that triggers an input capture event, select
the level that will be driven in response to an output compare match, or select the polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general purpose I/O pin not related to any timer
functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin
available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does
not require the use of a pin.
CPWMS
X
0
1
Table 15-6. Mode, Edge, and Level Selection
MSnB:MSnA
XX
00
01
1X
XX
ELSnB:ELSnA
00
01
10
11
01
10
11
10
X1
10
X1
Mode
Configuration
Pin not used for TPM - revert to general
purpose I/O or other peripheral control
Input capture
Capture on rising edge
only
Capture on falling edge
only
Capture on rising or
falling edge
Output compare
Toggle output on
compare
Clear output on
compare
Set output on compare
Edge-aligned
PWM
High-true pulses (clear
output on compare)
Low-true pulses (set
output on compare)
Center-aligned
PWM
High-true pulses (clear
output on compare-up)
Low-true pulses (set
output on compare-up)
15.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.
MC9S08DN60 Series Data Sheet, Rev 3
272
Freescale Semiconductor