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MC9S08DN60_08 Datasheet, PDF (268/356 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 15 Timer/PWM Module (S08TPMV3)
15.3 Register Deï¬nition
This section consists of register descriptions in address order.
15.3.1 TPM Status and Control Register (TPMxSC)
TPMxSC contains the overï¬ow status ï¬ag and control bits used to conï¬gure the interrupt enable, TPM
conï¬guration, clock source, and prescale factor. These controls relate to all channels within this timer
module.
7
6
5
4
3
2
1
0
R TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
W
0
Reset
0
0
0
0
0
0
0
0
Figure 15-7. TPM Status and Control Register (TPMxSC)
Table 15-2. TPMxSC Field Descriptions
Field
Description
7
Timer overï¬ow ï¬ag. This read/write ï¬ag is set when the TPM counter resets to 0x0000 after reaching the modulo
TOF value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control
register when TOF is set and then writing a logic 0 to TOF. If another TPM overï¬ow occurs before the clearing
sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed
for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a
previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overï¬ow
1 TPM counter has overï¬owed
6
TOIE
Timer overï¬ow interrupt enable. This read/write bit enables TPM overï¬ow interrupts. If TOIE is set, an interrupt is
generated when TOF equals one. Reset clears TOIE.
0 TOF interrupts inhibited (use for software polling)
1 TOF interrupts enabled
5
CPWMS
Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the
TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconï¬gures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS.
0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
MSnB:MSnA control bits in each channelâs status and control register.
1 All channels operate in center-aligned PWM mode.
4â3
CLKS[B:A]
Clock source selects. As shown in Table 15-3, this 2-bit ï¬eld is used to disable the TPM system or select one of
three clock sources to drive the counter prescaler. The ï¬xed system clock source is only meaningful in systems
with a PLL-based or FLL-based system clock. When there is no PLL or FLL, the ï¬xed-system clock source is the
same as the bus rate clock. The external source is synchronized to the bus clock by TPM module, and the ï¬xed
system clock source (when a PLL or FLL is present) is synchronized to the bus clock by an on-chip
synchronization circuit. When a PLL or FLL is present but not enabled, the ï¬xed-system clock source is the same
as the bus-rate clock.
2â0
PS[2:0]
Prescale factor select. This 3-bit ï¬eld selects one of 8 division factors for the TPM clock input as shown in
Table 15-4. This prescaler is located after any clock source synchronization or clock source selection so it affects
the clock source selected to drive the TPM system. The new prescale factor will affect the clock source on the
next system clock cycle after the new value is updated into the register bits.
MC9S08DN60 Series Data Sheet, Rev 3
268
Freescale Semiconductor
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