MC9S08DN60_08 Datasheet, PDF (287/356 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 16
Development Support
16.1 Introduction
Development support systems in the HCS08 include the background debug controller (BDC) and the
on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that
provides a convenient interface for programming the on-chip Flash and other nonvolatile memories. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
In the HCS08 Family, address and data bus signals are not available on external pins (not even in test
modes). Debug is done through commands fed into the target MCU via the single-wire background debug
interface. The debug module provides a means to selectively trigger and capture bus information so an
external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis
without having external access to the address and data signals.
16.1.1 Forcing Active Background
The method for forcing active background mode depends on the specific HCS08 derivative. For the
MC9S08DN60, you can force active background after a power-on reset by holding the BKGD pin low as
the device exits the reset condition. You can also force active background by driving BKGD low
immediately after a serial background command that writes a one to the BDFR bit in the SBDFR register.
If no debug pod is connected to the BKGD pin, the MCU will always reset into normal operating mode.
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor
287