MC9S08DN60_08 Datasheet, PDF (22/356 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 Device Overview
TPM1CLK TPM2CLK
1 kHZ
LPO
RTC
COP
TPM1
TPM2
IIC
SCI1
SPI
MCGERCLK
MCGIRCLK
MCG
MCGFFCLK
÷2
FFCLK*
MCGOUT
MCGLCLK
÷2 ^BUSCLK
XOSC
CPU
BDC
ADC
FLASH EEPROM
EXTAL XTAL
* The fixed frequency clock (FFCLK) is internally
synchronized to the bus clock and must not exceed one half
of the bus clock frequency.
ADC has min and max
frequency requirements.
See the ADC chapter
and electricals appendix
for details.
Figure 1-2. MC9S08DN60 System Clock Distribution Diagram
Flash and EEPROM have
frequency requirements
for program and erase
operation. See
the electricals appendix
for details.
MC9S08DN60 Series Data Sheet, Rev 3
22
Freescale Semiconductor