MC9S08DN60_08 Datasheet, PDF (211/356 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 11 Inter-Integrated Circuit (S08IICV2)
Clear
IICIF
Y
Master
N
Mode
?
TX
Tx/Rx
RX
?
Last Byte
Transmitted
Y
?
N
RXAK=0
?
N
Y
Last
Byte to Be Read _Y
?
N
End of
Y _{Addr Cycle}
(Master Rx)
?
N
Write Next
Byte to IICD
Y
2nd Last
Byte to Be Read
?
N
Set TXACK =1
Generate
Stop Signal
(MST = 0)
Switch to
Rx Mode
Clear ARBL
Y Arbitration
Lost
?
N
N
Y
(Read)
IAAS=1
?
Y
IAAS=1
?
Y
Address Transfer
See Note 1
N
Data Transfer
See Note 2
SRW=1
?
N ^(Write)
TX/RX
RX
?
TX
Set TX
Mode
Write Data
to IICD
Y ACK from
Receiver
?
N
Tx Next
Byte
Read Data
from IICD
and Store
Set RX
Mode
Switch to
Rx Mode
Dummy Read
from IICD
Generate
Stop Signal
(MST = 0)
Read Data
from IICD
and Store
Dummy Read
from IICD
Dummy Read
from IICD
RTI
NOTES:
1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a
general call address, then the general call must be handled by user software.
2. When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address. User software must ensure that for
this interrupt, the contents of IICD are ignored and not treated as a valid data transfer
Figure 11-12. Typical IIC Interrupt Routine
MC9S08DN60 Series Data Sheet, Rev 3
Freescale Semiconductor
211