M68HC12B Datasheet, PDF (284/334 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ATD)
Table 17-4. Multichannel Mode Result Register Assignment (Continued) (Continued)
S8CM CD CC CB CA
Channel Signal
Result in ADRx
if MULT = 1
0
0
0
Reserved
ADR0
0
0
1
Reserved
ADR1
0
1
0
Reserved
ADR2
0
1
1
1
1
1
0
0
Reserved
V_RH
ADR3
ADR4
1
0
1
V_RL
ADR5
1
1
0
(V_RH + V_RL)/2
ADR6
1
1
1
Test/reserved
ADR7
Shaded bits are “don’t care” if MULT = 1 and the entire block of four or eight channels makes
up a conversion sequence. When MULT = 0, all four bits (CD, CC, CB, and CA) must be
specified and a conversion sequence consists of four or eight consecutive conversions of
the single specified channel.
17.3.7 ATD Status Registers
Address: $0066
Bit 7
6
5
4
3
2
1
Bit 0
Read: SCF
0
0
0
0
CC2
CC1
CC0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 17-8
Address: $0067
Bit 7
Read: CCF7
Write:
Reset: 0
6
CCF6
5
CCF5
0
0
= Unimplemented
4
CCF4
0
3
CCF3
0
2
CCF2
0
1
CCF1
0
Bit 0
CCF0
0
Figure 17-9. ATD Status Register (ATDSTAT)
Read: Normally anytime
Write: In special mode, the SCF bit and the CCF bits may also be written.
The ATD status registers contain the flags indicating the completion of ATD conversions.
SCF — Sequence Complete Flag
This bit is set at the end of the conversion sequence when in the single conversion sequence mode
(SCAN = 0 in ATDCTL5) and is set at the end of the first conversion sequence when in the continuous
conversion mode (SCAN = 1 in ATDCTL5). When AFFC = 0, SCF is cleared when a write is performed
to ATDCTL5 to initiate a new conversion sequence. When AFFC = 1, SCF is cleared after the first
result register is read.
M68HC12B Family Data Sheet, Rev. 9.1
284
Freescale Semiconductor