M68HC12B Datasheet, PDF (152/334 Pages) Freescale Semiconductor, Inc – Microcontrollers

Standard Timer (TIM)
PAEN — Pulse Accumulator System Enable Bit
0 = Pulse accumulator system disabled
1 = Pulse accumulator system enabled
PAEN is independent from TEN.
PAMOD — Pulse Accumulator Mode Bit
0 = Event counter mode
1 = Gated time accumulation mode
PEDGE — Pulse Accumulator Edge Control Bit
For PAMOD = 0 (event counter mode)
0 = Falling edges on the pulse accumulator input pin (PT7/PAI) cause the count to be incremented.
1 = Rising edges on the pulse accumulator input pin cause the count to be incremented.
For PAMOD = 1 (gated time accumulation mode)
0 = Pulse accumulator input pin high enables E ÷ 64 clock to pulse accumulator and the trailing
falling edge on the pulse accumulator input pin sets the PAIF flag.
1 = Pulse accumulator input pin low enables E ÷ 64 clock to pulse accumulator and the trailing rising
edge on the pulse accumulator input pin sets the PAIF flag.
If the timer is not active (TEN = 0 in TSCR), there is no ÷64 clock since the E ÷ 64 clock is generated
by the timer prescaler.
CLK1 and CLK0 — Clock Select Bits
Table 12-4. Clock Selection
CLK1
0
0
1
1
CLK0
0
1
0
1
Selected Clock
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as
an input clock to the timer counter. The change from one selected clock to the other happens
immediately after these bits are written.
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
0 = Interrupt inhibited
1 = Interrupt requested if PAOVF is set
PAI — Pulse Accumulator Input Interrupt Enable Bit
0 = Interrupt inhibited
1 = Interrupt requested if PAIF is set
M68HC12B Family Data Sheet, Rev. 9.1
152
Freescale Semiconductor