M68HC12B Datasheet, PDF (208/334 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Interface
form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is
serially shifted eight bit positions by the SCK clock from the master so the data is exchanged effectively
between the master and the slave.
NOTE
Some slave devices are simple and either accept data from the master
without returning data to the master or pass data to the master without
requiring data from the master.
14.4 Port S
In all modes, port S bits PS7–PS0 can be used for either general-purpose I/O or with the SCI and SPI
subsystems. During reset, port S pins are configured as high-impedance inputs (DDRS is cleared).
14.4.1 Port S Data Register
Address:
Read:
Write:
Pin Function
Reset:
$00D6
Bit 7
6
5
4
3
2
1
PS7
PS6
PS5
PS4
PS3
PS2
PS1
SS
CS
SCK
MOSI
MOMI
MISO
SISO
—
—
TXD0
After reset all bits configured as general-purpose inputs
Figure 14-20. Port S Data Register (PORTS)
Bit 0
PS0
RXD0
Read: Anytime; inputs return pin level; outputs return pin driver input level
Write: Data stored in internal latch; drives pins only if configured for output; does
not change pin state when pin configured for SPI or SCI output
Port S shares function with the on-chip serial systems, SPI0 and SCI0.
14.4.2 Port S Data Direction Register
Address:
Read:
Write:
Reset:
$00D7
Bit 7
DDS7
0
6
DDS6
0
5
DDS5
0
4
DDS4
0
3
DDS3
0
2
DDS2
0
1
DDS1
0
Bit 0
DDS0
0
Figure 14-21. Port S Data Direction Register (DDRS)
Read: Anytime
Write: Anytime
After reset, all general-purpose I/O are configured for input only.
0 = Configure the corresponding I/O pin for input only.
1 = Configure the corresponding I/O pin for output.
M68HC12B Family Data Sheet, Rev. 9.1
208
Freescale Semiconductor