M68HC12B Datasheet, PDF (135/334 Pages) Freescale Semiconductor, Inc – Microcontrollers

PWM Register Descriptions
11.2.11 PWM Channel Duty Registers 0–3
Address: $0050
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 11-20. PWM Channel Duty Register 0 (PWDTY0)
Address: $0051
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 11-21. PWM Channel Duty Register 1 (PWDTY1)
Address: $0052
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 11-22. PWM Channel Duty Register 2 (PWDTY2)
Address: $0053
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 11-23. PWM Channel Duty Register 3 (PWDTY3)
Read: Anytime
Write: Anytime
The value in each duty register determines the duty of the associated PWM channel. When the duty value
is equal to the counter value, the output changes state. If the register is written while the channel is
enabled, the new value is held in a buffer until the counter rolls over or the channel is disabled. Reading
this register returns the most recent value written.
If the duty register is greater than or equal to the value in the period register, there is no duty change in
state. If the duty register is set to $FF, the output is always in the state which would normally be the state
opposite the PPOLx value.
Left-aligned output mode (CENTR = 0):
Duty cycle = [(PWDTYx + 1) / (PWPERx + 1)] × 100%(PPOLx = 1)
Duty cycle = [(PWPERx − PWDTYx) / (PWPERx + 1)] × 100%(PPOLx = 0)
Center-aligned output mode (CENTR = 1):
Duty cycle = [(PWPERx − PWDTYx) / PWPERx] × 100%(PPOLx = 0)
Duty cycle = (PWDTYx / PWPERx) × 100%(PPOLx = 1)
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
135