M68HC12B Datasheet, PDF (265/334 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmer’s Model of Control Registers
16.12.4 msCAN12 Bus Timing Register 1
Address: $0103
Bit 7
Read:
SAMP
Write:
Reset: 0
6
TSEG22
0
5
TSEG21
0
4
TSEG20
0
3
TSEG13
0
2
TSEG12
0
1
TSEG11
0
Figure 16-19. msCAN12 Bus Timing Register 1 (CBTR1)
Bit 0
TSEG10
0
SAMP — Sampling Bit
This bit determines the number of samples of the serial bus to be taken per bit time. If set, three
samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority
rule. For higher bit rates, SAMP should be cleared, which means that only one sample will be taken
per bit.
0 = One sample per bit
1 = Three samples per bit.⁽¹⁾
TSEG22–TSEG10 — Time Segment Bits
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point. See Figure 16-7.
Table 16-7. Time Segment Syntax
SYNC_SEG
Transmit point
Sample point
System expects transitions to occur on the bus during this period.
A node in transmit mode will transfer a new value to the CAN bus at this point.
A node in receive mode will sample the bus at this point. If the three samples per bit option is
selected, then this point marks the position of the third sample.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 16-8.
Table 16-8. Time Segment Values
TSEG13
0
0
0
0
.
1
TSEG12
0
0
0
0
.
1
TSEG11
0
0
1
1
.
1
TSEG10
0
1
0
1
.
1
Time Segment 1
1 Tq clock cycle
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
.
16 Tq clock cycles
TSEG22
0
0
.
1
TSEG21
0
0
.
1
TSEG20
0
1
.
1
Time Segment 2
1 Tq clock cycle
2 Tq clock cycles
.
8 Tq clock cycles
1. In this case, PHASE_SEG1 must be at least two times quanta.
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
265