M68HC12B Datasheet, PDF (196/334 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Interface
RSRC — Receiver Source Bit
When LOOPS = 1, the RSRC bit determines the internal feedback path for the receiver.
0 = Receiver input connected to the transmitter internally
(not TXD pin)
1 = Receiver input connected to the TXD pin
M — Mode Bit (select character format)
0 = One start, eight data, one stop bit
1 = One start, eight data, ninth data, one stop bit
WAKE — Wakeup by Address Mark/Idle Bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (last data bit set)
ILT — Idle Line Type Bit
This bit determines which of two types of idle line detection is used by the SCI receiver.
0 = Short idle line mode enabled
1 = Long idle line mode detected
In short mode, the SCI circuitry begins counting 1s in the search for the idle line condition immediately
after the start bit. This means that the stop bit and any bits that were 1s before the stop bit could be
counted in that string of 1s, resulting in earlier recognition of an idle line.
In long mode, the SCI circuitry does not begin counting 1s in the search for the idle line condition until
a stop bit is received. Therefore, the last byte’s stop bit and preceding 1 bits do not affect how quickly
an idle line condition can be detected.
PE — Parity Enable Bit
0 = Parity disabled
1 = Parity enabled
PT — Parity Type Bit
If parity is enabled, this bit determines even or odd parity for both the receiver and the transmitter. An
even number of 1s in the data character causes the parity bit to be 0 and an odd number of 1s causes
the parity bit to be 1.
0 = Even parity selected
1 = Odd parity selected
M68HC12B Family Data Sheet, Rev. 9.1
196
Freescale Semiconductor