M68HC12B Datasheet, PDF (146/334 Pages) Freescale Semiconductor, Inc – Microcontrollers

Standard Timer (TIM)
Address: $008A
Bit 7
Read:
EDG7B
Write:
Reset: 0
6
EDG7A
0
5
EDG6B
0
4
EDG6A
0
3
EDG5B
0
2
EDG5A
0
1
EDG4B
0
Figure 12-10. Timer Control Register 3 (TCTL3)
Bit 0
EDG4A
0
Address: $008B
Bit 7
6
5
4
3
2
1
Read:
Write:
Reset:
EDG3B
0
EDG3A
0
EDG2B
0
EDG2A
0
EDG1B
0
EDG1A
0
EDG0B
0
Figure 12-11. Timer Control Register 4 (TCTL4)
Bit 0
EDG0A
0
Read: Anytime
Write: Anytime
EDGnB and EDGnA — Input Capture Edge Control Bits
These 8 pairs of control bits configure the input capture edge detector circuits. See Table 12-2.
Table 12-2. Edge Detector Circuit Configuration
EDGnB
0
0
1
1
EDGnA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
12.3.7 Timer Interrupt Mask Registers
Address: $008C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 12-12. Timer Interrupt Mask 1 Register (TMSK1)
Read: Anytime
Write: Anytime
The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the
corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled
to cause a hardware interrupt.
M68HC12B Family Data Sheet, Rev. 9.1
146
Freescale Semiconductor