M68HC12B Datasheet, PDF (226/334 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Communications (BDLC)
200 µs
128 µs
64 µs
ACTIVE
(1) INVALID ACTIVE BIT
PASSIVE
A
ACTIVE
(2) VALID ACTIVE LOGIC 1
PASSIVE
A
B
ACTIVE
(3) VALID ACTIVE LOGIC 0
PASSIVE
ACTIVE
B
C
(4) VALID SOF SYMBOL
PASSIVE
C
D
Figure 15-8. J1850 VPW Received Active Symbol Times
15.7.4.7 Invalid Active Bit
In Figure 15-8(1), if the active-to-passive received transition beginning the next data bit (or symbol) occurs
between the passive-to-active transition beginning the current data bit (or symbol) and A, the current bit
would be invalid.
15.7.4.8 Valid Active Logic 1
In Figure 15-8(2), if the active-to-passive received transition beginning the next data bit (or symbol) occurs
between A and B, the current bit would be considered a logic 1.
15.7.4.9 Valid Active Logic 0
In Figure 15-8(3), if the active-to-passive received transition beginning the next data bit (or symbol) occurs
between B and C, the current bit would be considered a logic 0.
15.7.4.10 Valid SOF Symbol
In Figure 15-8(4), if the active-to-passive received transition beginning the next data bit (or symbol) occurs
between C and D, the current symbol would be considered a valid SOF symbol.
M68HC12B Family Data Sheet, Rev. 9.1
226
Freescale Semiconductor