M68HC12B Datasheet, PDF (104/334 Pages) Freescale Semiconductor, Inc – Microcontrollers

FLASH EEPROM
8.4.3.2 Program/Erase Verification
When programming or erasing the FLASH EEPROM array, a special verification method is required to
ensure that the program/erase process is reliable and also to provide the longest possible life expectancy.
This method requires stopping the program/erase sequence at periods of t_PPULSE (t_EPULSE for erasing)
to determine if the FLASH EEPROM is programmed/erased. After the location reaches the proper value,
it must continue to be programmed/erased with additional margin pulses to ensure that it will remain
programmed/erased. Failure to provide the margin pulses could lead to corrupted or unreliable data.
8.4.3.3 Program/Erase Sequence
To begin a program or erase sequence, the external V_FP voltage must be applied and stabilized. The
ERAS bit must be set or cleared, depending on whether a program sequence or an erase sequence is to
occur. The LAT bit will be set to cause any subsequent data written to a valid address within the FLASH
EEPROM to be latched into the programming address and data latches. The next FLASH array write cycle
must be either to the location that is to be programmed if a programming sequence is being performed,
or, if erasing, to any valid FLASH EEPROM array location. Writing the new address and data information
to the FLASH EEPROM is followed by assertion of ENPE to turn on the program/erase voltage to
program/erase the new location(s). The LAT bit must be asserted and the address and data latched to
allow the setting of the ENPE control bit. If the data and address have not been latched, an attempt to
assert ENPE will be ignored and ENPE will remain negated after the write cycle to FEECTL is completed.
The LAT bit must remain asserted and the ERAS bit must remain in its current state as long as ENPE is
asserted. A write to the LAT bit to clear it while ENPE is set will be ignored. That is, after the write cycle,
LAT will remain asserted. Likewise, an attempt to change the state of ERAS will be ignored and the state
of the ERAS bit will remain unchanged.
The programming software is responsible for all timing during a program sequence. This includes the total
number of program pulses (n_PP), the length of the program pulse (t_PPULSE), the program margin pulses
(p_m) and the delay between turning off the high voltage and verifying the operation (t_VPROG).
The erase software is responsible for all timing during an erase sequence. This includes the total number
of erase pulses (e_m), the length of the erase pulse (t_EPULSE), the erase margin pulse or pulses, and the
delay between turning off the high voltage and verifying the operation (t_VERASE).
Software also controls the supply of the proper program/erase voltage to the V_FP pin and should be at the
proper level before ENPE is set during a program/erase sequence.
A program/erase cycle should not be in progress when starting another program/erase or while
attempting to read from the array.
NOTE
Although clearing ENPE disables the program/erase voltage (V_FP) from the
V_FP pin to the array, care must be taken to ensure that V_FP is at V_DD
whenever programming/erasing is not in progress. Not doing so could
damage the part. Ensuring that V_FP is always greater or equal to V_DD can
be accomplished by controlling the V_FP power supply with the programming
software via an output pin. Alternatively, all programming and erasing can
be done prior to installing the device on an application circuit board which
can always connect V_FP to V_DD. Programming can also be accomplished
by plugging the board into a special programming fixture which provides
program/erase voltage to the V_FP pin.
M68HC12B Family Data Sheet, Rev. 9.1
104
Freescale Semiconductor