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MC33662LEF Datasheet, PDF (14/31 Pages) Freescale Semiconductor, Inc – LIN 2.1 / SAEJ2602-2, LIN Physical Layer
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
TBIT
TBIT
VLIN_REC
THREC(MAX)74.4% VSUP
THDOM(MAX) 58.1% VSUP
LIN
THREC(MIN) 42.2% VSUP
THDOM(MIN) 28.4% VSUP
tBUS_DOM(MAX)
tBUS_REC(MIN)
Thresholds of
receiving node 1
Thresholds of
receiving node 2
RXD
Output of receiving Node 1
tREC_PDF(1)
RXD
Output of receiving Node 2
tBUS_DOM(MIN)
tREC_PDR(2)
tBUS_REC(MAX)
tREC_PDR(1)
tREC_PDF(2)
Figure 9. LIN Timing Measurements for Normal Baud Rate (33662L and 33662S)
TXD
TBIT
TBIT
VLIN_REC
THREC(MAX)77.8% VSUP
THDOM(MAX) 61.6% VSUP
LIN
THREC(MIN) 38.9% VSUP
THDOM(MIN) 25.1% VSUP
tBUS_DOM(MAX)
tBUS_REC(MIN)
RXD
Output of receiving Node 1
tREC_PDF(1)
RXD
Output of receiving Node 2
tBUS_DOM(MIN)
tREC_PDR(2)
tBUS_REC(MAX)
tREC_PDR(1)
tREC_PDF(2)
Figure 10. LIN Timing Measurements for Slow Baud Rate (33662J)
Thresholds of
receiving node 1
Thresholds of
receiving node 2
33662
14
Analog Integrated Circuit Device Data
Freescale Semiconductor