MC33662LEF Datasheet, PDF (11/31 Pages) Freescale Semiconductor, Inc – LIN 2.1 / SAEJ2602-2, LIN Physical Layer

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics
Characteristics under conditions 7.0 V  V_SUP  18 V, - 40C  T_A  125C, GND = 0 V, unless otherwise noted. Typical
values reflect the approximate parameter means at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER
DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION^{(15), (16)}
33662L AND 33662S DEVICES
Duty Cycle 1:
TH_REC(MAX) = 0.744 * V_SUP
TH_DOM(MAX) = 0.581 * V_SUP
D1 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT = 50 µs, 7.0 V V_SUP18 V
D1
0.396
—
%
—
Duty Cycle 2:
TH_REC(MIN) = 0.422 * V_SUP
TH_DOM(MIN) = 0.284 * V_SUP
D2 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT = 50 µs, 7.6 V V_SUP18 V
D2
—
—
0.581
LIN PHYSICAL LAYER
DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION^{(15), (16)}
33662J DEVICE
Duty Cycle 3:
TH_REC(MAX) = 0.778 * V_SUP
TH_DOM(MAX) = 0.616 * V_SUP
D3 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT = 96 µs, 7.0 V V_SUP18 V
D3
0.417
—
%
—
Duty Cycle 4:
TH_REC(MIN) = 0.389 * V_SUP
TH_DOM(MIN) = 0.251 * V_SUP
D4 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT = 96 µs, 7.6 V V_SUP18 V
D4
—
—
0.590
LIN PHYSICAL LAYER
DRIVER CHARACTERISTICS FOR FAST SLEW RATE
Fast Bit Rate (Programming Mode)
BR_FAST
—
LIN PHYSICAL LAYER
TRANSMITTER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC⁽¹⁹⁾
33662S DEVICE
—
100
kBit/s
Symmetry of Transmitter delay⁽¹⁸⁾
t_{TRAN_SYM} = MAX (t_{TRAN_SYM60%}, t_{TRAN_SYM40%})
t_{TRAN_SYM60%} = | t_{TRAN_PDF60% -} t_{TRAN_PDR60%} |
t_{TRAN_SYM40%} = | t_{TRAN_PDF40% -} t_{TRAN_PDR40%} |
s
t _{TRAN_SYM}
-7.25
—
7.25
Notes
15. Bus load R_BUS and C_BUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal
threshold defined at each parameter. See Figure 8.
16. See Figure 9.
17. See Figure 10.
18. See Figure 11
19. V_SUP from 7.0 to 18 V, bus load R_BUS and C_BUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 8.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33662
11