MC33662LEF Datasheet, PDF (12/31 Pages) Freescale Semiconductor, Inc – LIN 2.1 / SAEJ2602-2, LIN Physical Layer

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics under conditions 7.0 V  V_SUP  18 V, - 40C  T_A  125C, GND = 0 V, unless otherwise noted. Typical
values reflect the approximate parameter means at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
LIN PHYSICAL LAYER
RECEIVER CHARACTERISTICS ACCORDING LIN2.1⁽²⁰⁾
33662L AND 33662J AND 33662S DEVICES
Propagation Delay and Symmetry⁽²¹⁾
Propagation Delay of Receiver, t_{REC_PD} = MAX (t_{REC_PDR}, t_{REC_PDF})
Symmetry of Receiver Propagation Delay, t_{REC_PDF} - t_{REC_PDR}
Symbol
Min
Typ
Max
Unit
s
t _{REC_PD}
—
—
6.0
t _{REC_SYM}
- 2.0
—
2.0
LIN PHYSICAL LAYER
RECEIVER CHARACTERISTICS WITH TIGHTEN LIMITS⁽²²⁾
33662S DEVICE
Propagation Delay and Symmetry⁽²³⁾
s
Propagation Delay of Receiver, t_{REC_PD} = MAX (t_{REC_PDR}, t_{REC_PDF})
t _{REC_PD_S}
—
—
5.0
Symmetry of Receiver Propagation Delay, t_{REC_PDF} - t_{REC_PDR}
t _{REC_SYM_S}
- 1.3
—
1.3
LIN PHYSICAL LAYER
RECEIVER CHARACTERISTICS - LIN SLOPE 1.0 V/ns⁽²²⁾
33662S DEVICE
Propagation Delay and Symmetry⁽²⁴⁾
s
Propagation Delay of Receiver, t_{REC_PD _FAST}= MAX (t_{REC_PDR_FAST},
t _{REC_PD_FAST}
—
—
6.0
t_{REC_PDF_FAST})
Symmetry of Receiver Propagation Delay, t_{REC_PDF_FAST} - t_{REC_PDR_FAST} ^tREC_SYM_FAST
- 1.3
—
1.3
SLEEP MODE AND WAKE-UP TIMINGS
Sleep Mode Delay Time ⁽²⁵⁾
after EN High to Low to INH High to Low with 100 µA load on INH
t _SD
µs
50
—
91
WAKE-UP TIMINGS
Bus Wake-up Deglitcher (Sleep Mode) ⁽²⁶⁾
EN Wake-up Deglitcher ⁽²⁷⁾
EN High to INH Low to High
Wake-up Deglitcher ⁽²⁸⁾
Wake state change to INH Low to High
t _WUF
40
70
100
s
t _LWUE
s
—
—
15
t _WF
s
10
48
70
TXD TIMING
TXD Permanent Dominant State Delay⁽²⁹⁾
t _TXDDOM
3.75
5.0
6.25
ms
FIRST DOMINANT BIT VALIDATION
First dominate bit validation delay when device in Normal Mode⁽³⁰⁾
t _{FIRST_DOM}
—
50
80
µs
Notes
20. V_SUP from 7.0 to 18 V, bus load R_BUS and C_BUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 8.
21. See Figure 12.
22. V_SUP from 7.0 to 18 V, bus load R_BUS and C_BUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 8.
23. See Figure 12
24. See Figure 13
25. See Figure 25 and 26
26. See Figure 16, 19, and Figure 20
27. See Figure 14, 17, Figure 21, Figure 25 and Figure 26
28. See Figure 15, 18, Figure 25 and Figure 26
29. The LIN is in recessive state and the receiver is still active.
30. See Figure 14, 17, 15, 18, 16, 19 and Figure 24
33662
12
Analog Integrated Circuit Device Data
Freescale Semiconductor