MC81F4332 Datasheet, PDF (37/198 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC81F4x16
Shift
Clock
Data
Out
Data
In
tSCK
tS1
D0
tS2
Valid
tH1
D1
D2
tH2
Valid
Valid
D3
Valid
D4
D5
Valid
Valid
D6
Valid
D7
Valid
NOTE: The symbols shown in this diagram are defined as follows:
fSCK
Serial port clock cycle time
tS1
Output data setup to clock rising edge
tS2
Clock rising edge to input data valid
tH1
Output data hold after clock rising edge
tH2
Input data hold after clock rising edge
Figure 7-7 Timing Waveform for the UART Module
October 19, 2009 Ver.1.35
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