MC81F4332 Datasheet, PDF(165/198 Page) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

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MC81F4332 Datasheet, PDF (165/198 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

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25.4 Procedure

Initialization

Following steps initialize the IIC slave.

MC81F4432

1. Set SCL and SDA pins as an alternative mode.

Set the R1CONH[7~4] bits by â1010bâ.

2. Set the slave address by setting the IICAR register.

3. Enable IIC module and the interrupt :

Set the ACKE bit by â1â

Set the IICEN bit by â1â

Set the IICIFEN bit by â1â. ( If it is cleared by â0â, IIC interrupt is not occurred )

-> Or you can simply set the IICSCR register by âE0hâ.

After finish above steps, IIC interrupt is enabled. So The IIC interrupt will be generated after receive

or transmit one byte.

Interrupt Routine Procedure

Simply say, when you write a byte to the IICDSR, it is transmitted and when a byte is received, you

can read it from the IICDSR register.

But, the master has a right to decide the read/write mode. And the master sends 1-bit R/W mode flag

after 7-bit slave address. And it is stored in the IICTR(IICSCR.3) bit when it is received.

So you can recognize current Rx/Tx mode. And you have to react based on the IICTR(IICSCR.3) bit.

The IICTR(IICSCR.3) bit equals â1â means that the master want to read from the slave. So, In this

case, Slave-IICâs mode is changed into âtransmit modeâ automatically. So, in this case you have to

write a data to the IICDSR register as you want.

The IICTR(IICSCR.3) bit equals â0â means that the master want to write to the slave. So, In this case,

Slave-IICâs mode is changed into âreceive modeâ automatically. So, in this case you have to read a

data from the IICDSR register.

Before finish the IIC interrupt routine, you have to clear the IICIF bit. When the IICIF bit is cleared, the

SCL line is released. If it is not cleared, the SCL line is holding down to low status. While in this

condition, master canât continue the IIC communication.

In order to recognize current received byteâs position in the message, you have to count the IIC

interrupts. Based on the position information

October 19, 2009 Ver.1.35

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