MC81F4332 Datasheet, PDF (121/198 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

18.4 Timer 0 16-BIT Mode
MC81F4432
T0CS
fxx/2048
fxx/512
fxx/128
fxx/32
fxx/16
fxx/8
fxx/4
fxx/2
fxt
EC0
Counter stop
M
EXT1
U
X
Data BUS
T0OVIE
Timer 0 overflow INT enable
OVF
T0OVIR
T0 Overflow
M
T1CR
8
T0CR
Timer 0 Overflow INT request
Interrupt
U
16-Bit Up Counter
(Read - only)
R
Clear
X
T0OVIF
T0CC
Match signal
Clear
T0MIE
16-Bit Comparator
Match ^M
U
X
Timer 0 INT enable
T0MIR
Timer 0 Match INT request
T0O/PWM0O
T0 Match
Interrupt
Timer 0 Buffer Register
T0MS
T0MIF
EINT0L
Timer 1 + Timer 0
MSB Timer 0 Data Register LSB
T1DR
T0DR
EXT1
8
Interrupt
Data BUS
Timer 0 (16bit)
T0CC
Overflow signal
Match signal
Figure 18-3 16-bit Timer 0 Block Diagram
The 16-bit timer 0 is a 16-bit general-purpose timer. Timer 0 has three operating modes, you can
select one of them using the appropriate T0SCR setting:
- Interval timer mode (Toggle output at T0O pin)
- Capture input mode with a rising or falling edge trigger at EXT1 pin
- PWM mode (PWM0O)
The 16-bit timer 0 has the following functional components:
- Clock frequency divider (fxx divided by 2048, 512, 128, 32, 16, 8, 4, 2, fxt) with multiplexer
- External clock input pin, EC0 (R02)
- I/O pins for capture input, EXT1 (R03) or PWM or match output PWM0O/T0O (R03)
- 16-bit counter (T0CR+T1CR), 16-bit comparator, and 16-bit reference data register
(T0DR+T1DR)
- Timer 0 status and control register (T0SCR)
- Timer 0 overflow interrupt and match interrupt generation
October 19, 2009 Ver.1.35
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