MC81F4332 Datasheet, PDF (147/198 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

23.1 Registers
MC81F4432
SIOCR
SERIAL I/O INTERFACE CONTROL REGISTER
00E7H
A reset clears the SIOCR register value to "00H". Whit this value, internal clock source and receive-
only mode are selected and the 3-bit counter is cleared. The data shift operation is disabled. The
selected data direction is MSB-first.
SIOCR
7
6
5
4
3
2
1
0
–
– CSEL DAT SIOM SIOP CCLR SEDGE Reset value:
–
– R/W R/W R/W R/W R/W R/W
--00_0000b
–
CSEL
bit7 – bit6
SIO Shift Clock Selection Bit
DAT
Data Direction Control Bit
SIOM
SIO Mode Selection Bit
SIOP
SIO Shift Operation Enable Bit
CCLR SIO Counter Clear and Shift Start Bit
SEDGE Shift Clock Edge Selection Bit
Not used for MC81F4x32
0: Internal clock (P.S clock)
1: External clock (SCK)
0: MSB-first mode
1: LSB-first mode
0: Receive only mode
1: Transmit/Receive mode
0: Disable shifter and clock counter
1: Enable shifter and clock counter
0: No action
1: Clear 3-bit counter and start shifting
0: Tx at falling edges, Rx at rising edges
1: Tx at rising edges, Rx at falling edges
SIODAT
SIO DATA REGISTER
00E8H
SIODAT
7
6
5
4
3
2
1
0
One byte register
Reset value: 00H
R/W R/W R/W R/W R/W R/W R/W R/W
A 8-bit data register for SIO Rx/Tx data
SIOPS
SIO PRE-SCALER REGISTER
00E9H
SIOPS
7
6
5
4
3
2
1
0
One byte register
Reset value: 00H
R/W R/W R/W R/W R/W R/W R/W R/W
Baud rate = (fxx/4) / (SIOPS+1)
October 19, 2009 Ver.1.35
147