MC81F4332 Datasheet, PDF (175/198 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

27.3 Sleep vs Stop
MC81F4432
Peripheral
STOP
in Main OSC
STOP
in SUB OSC
SLEEP Mode
CPU
Stop
Stop
RAM
Retain
Retain
I/O Ports
Retain
Retain
Control Registers
Retain
Retain
Address Data Bus
Retain
Retain
ADC
Stop
Operate
Usart
Stop
Operate
SIO
Only operated with external clock
Operate
IIC Slave
Operate
Operate
Basic Interval Timer
Stop
Operate
Watchdog Timer
Stop
Operate
Watch Timer with System clock
Stop
Operate
Timer/Counter with System clock
Stop
Operate
Buzzer
with System clock
Stop
Operate
Watch Timer with Sub clock
Operate
Stop
Operate
Timer/Counter with Sub clock
Operate
Stop
Operate
Buzzer
with Sub clock
Operate
Stop
Operate
Main Oscillator
Stop
Oscillation
Oscillation
Sub Oscillator
Oscillation
Stop
Oscillation
Release Source
Reset, Timer(0,1,2,3)
,Watch Timer(with Sub clock)
, SIO, USART, IIC Slave
,External Interrupt
Reset, All Interrupts
Table 27-1 Peripheral Operation During Power Saving Mode
Note:
In the stop mode, system clock source is stopped. But unselected clock source is not
stopped.
For example, when main oscillator is selected as the system clock and the stop instruction is
executed, main oscillator is stopped, but sub oscillator is not stopped. (assume that, both
oscillator are working before stop instruction) In this case, the watch timer can be operated
with sub oscillator.
October 19, 2009 Ver.1.35
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