MC81F4332 Datasheet, PDF (161/198 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC81F4432
IICSCR
SLAVE IIC STATUS AND CONTROL REGISTER
7
6
5
4
3
IICSCR
ACKE IICEN IICIFEN IICAZS IICTR
R/W R/W R/W R R/W
2
IICBS
R
1
SAM
R
0
IICLR
R
00E2H
Reset value: 00H
ACKE IIC-Bus Acknowledgement Enable Bit
IICEN IIC-Bus Module Enable Bit
IICIFEN IICIF Enable/Disable Bit
IICAZS IIC-Bus Address Zero Status Flag
IICTR Slave IIC-Bus Tx/Rx mode Status Bit
IICBS IIC-Bus Busy Status Bit
SAM
Slave Address Match Bit
IICLR
IIC-Bus Last Received Bit Status Bit
0: Disable ACK generation
1: Enable ACK generation
0: Disable IIC-Bus module
1: Enable IIC-Bus module
0: IICIF (interrupt flag) cannot be
generated and IIC interrupt is disabled.
1: IICIF (interrupt flag) can be generated
and IIC interrupt is also enabled.
0: It is cleared when start or stop
condition is generated.
1: It is set when received slave address
is 00H (general call)
It is set or cleared by W/R signal from
the master.
0: Slave Receive mode
1: Slave transmit mode
0: IIC-bus is not busy (It is cleared when
„stop‟ condition is received).
1: IIC-bus is busy (It is set when „start‟
condition is received).
0: It is cleared when start or stop or
reset condition is generation
1: When received slave address value
matches to „SIAR‟ register
0: Last-received 9th bit is “0” (ACK was
received)
1: Last-received 9th bit is “1” (ACK was
not received)
Note : The IICIFEN must be set by „1‟ to use IIC interrupt. If it is cleared by „0‟ IIC interrupt is
not occurred.
So, in order to use IIC interrupt, both IICIFEN(IICSCR.5) and IICEN(IENL.7) must be set by
„1‟.
October 19, 2009 Ver.1.35
161