MC81F4332 Datasheet, PDF (101/198 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC81F4432
13. CLOCK GENERATOR
MOSC
SCLK
STOP inst.
SSCR
‘01011010’ stop mode
SOSC
SCLK
STOP inst.
SSCR
‘01011010’ stop mode
Main
Oscillator Stop
Main-System
Oscillator
fx
Circuit
Stop release
INT
Sub
Oscillator Stop
Sub-System
Oscillator
Circuit
fxt
Watch Timer,
Timer 0/1/2/3,
Buzzer
Peripheral clock
SCLK
MUX
fxx
System clock
SSCR
‘00001111’ SLEEP mode
Frequency Dividing Circuit
1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 1/512 1/1024 1/2048 1/4096
Figure 13-1 Block Diagram of Clock Generator
As shown in Figure 13-1, the clock generator produces the basic clock pulses for the CPU and the
peripheral hardware.
It contains two oscillators which are main-system oscillator and a sub-oscillator. And for the system
and the peripheral clocks, one oscillator is selected by the SCLK bit of the OSCSEL register.
There are few clock sources for main-oscillator which are listed below.
- Crystal / Ceramic Oscillator / (External Clock).
- 8, 4, 2, 1 MHz Internal RC Oscillator.
- External RC Oscillator.
Note that, one of the clock sources is used for main-oscillator based on the ROM option (See „8 .
ROM OPTION‟ at page 47).
Only one clock source is available for sub-oscillator which is „Crystal / Ceramic Oscillator / (External
Clock )‟.
To the peripheral block, the clock among the not-divided original clocks and divided by 2, 4..., up to
4096 can be provided. Peripheral clock is enabled or disabled by STOP instruction.
When the system is fall in stop mode, only selected oscillator(by SCLK bit) is stopped. Unselected
oscillator is not affected by stop mode.
October 19, 2009 Ver.1.35
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