MC81F4332 Datasheet, PDF (169/198 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC81F4432
26.5 Power On Reset
There is a internal power on reset circuit internally. We simply call it POR. POR occurs the reset event
when VDD is rising over the POR level.
Note that, POR can be enabled and disabled by the PORC register. And default setting is „POR
enable‟. So at the first time power is supplied, POR is working always even external reset is enabled.
PORC
POWER ON RESET CONTROL REGISTER
7
6
5
4
3
2
PORC
One byte register
(00F3H)
1
0
Reset value:00H
POR Enable/Disable
01011010: POR disable
Others: POR enable
Note :
It is recommended to disable the POR. When POR is enabled, current consumption is
increased and, the LVR(Low Voltage Reset) is ignored even the LVR is enabled by the „ROM
OPTION‟.
26.6 Low Voltage Reset
Figure 26-4 LVR Timing Diagram at 4MHz system clock
The low voltage reset occurs the reset event when current VDD is going down under the LVR level.
It is configurable by the rom-option. ( See „8. ROM OPTION‟ on page 47)
If you want to know more detail timing information, see „7.9 LVR (Low Voltage Reset) Electrical
Characteristics‟ on page 36.
October 19, 2009 Ver.1.35
169