FMS7401L_05 Datasheet, PDF (9/81 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
FMS7401L
The BOR circuit should be used in situations when Vcc rises and falls slowly and in situations when Vcc does not fall to 0V
before rising back to the device’s normal operating range. The BOR circuit can be thought of as a supplement function to the
POR circuit if Vcc does not fall below 0.7V.
Figure 2. BOR and POR Circuit Relationship Diagram
Vcc (Pin 8)
BOR
output
VCC
7 1. 5
0
VCC
0
VCC
Time
BOR Output
POR
output
VCC
3.0V
7 (Pin )
3.0V
VCC⁰
POR
output ₀
Reset
A ^Circuit
Output
Global Reset
to oL gic
External
Reset
Pin
O l (14-Pin n y)
P ^Pu^Ols^Re^Output
B
The Reset r u t ci c i will trigger
when inputs A or B a o rt s t n i i n
from High to Low. At that time
the Global Reset signal will go
high which will reset all
controller logic. The Global
Reset will go high and stay
high for around 1µs.
1. Available only on the 14-pin package option.
2. Refer to the Timer 0 Circuit section of the datasheet for details regarding the Watchdog Reset.
3. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
4. Refer to the Device Memory section of the datasheet for details regarding the Initialization Register 1.
5. Refer to Table 28 and Table 29 of the Device Memory section of the datasheet for details.
REV. 1.0.3 1/24/05
9