FMS7401L_05 Datasheet, PDF (58/81 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
FMS7401L
Table 31. Memory Mapped Registers and their Register Bit Definitions
Address
Name¹⁰
Bit7
Definitions of Register Bits
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x9D
ADATA
8-bit digital value of ADC conversion
0x9F
ADCNTRL1
APND
AINTEN
ASTART
REFSEL
ACHSEL [3:0]
0xA0
ADCNTRL2
REFBY2 COMPSEL ENAMP
ENDAS
ASPEED [1:0]
ENIS
GAIN
0xA2
DDELAY
COMPEN
PWINT
EPWM OFFMODE
DD [3:0]
0xA4
PSCALE
PLLEN
FS [1:0]
FSEL
FMODE
PS [2:0]
0xA5
DTIME
X
X
X
DT [4:0]
0xA6
T1CMPALO
Low 8 bits of 12-bit T1CMPA register
0xA7
T1CMPAHI
X
X
X
X
High 4 bits of 12-bit T1CMPA register
0xA8
T1CMPBLO
Low 8 bits of 12-bit T1CMPB register
0xA9
T1CMPBHI
X
X
X
X
High 4 bits of 12-bit T1CMPB register
0xAA
T1RALO
Low 8 bits of 12-bit T1RA register
0xAB
T1RAHI
X
X
X
X
High 4 bits of 12-bit T1RA register
0xAC
TMR1LO
Low 8 bits of 12-bit TMR1 register
0xAD
TMR1HI
X
X
X
X
High 4 bits of 12-bit TMR1 register
0xAE
T1CNTRL
T1C3
T1C2
T1C1
T1C0
T1PND
T1EN
X
T1BOUT
0xAF
WKEDG
Bit number = port number, Edge direction
0xB0
WKPND
Bit number = port number, Pending flag for port
0xB1
WKEN
Bit number = port number, Interrupt enable for port
0xB2
PORTGD
Bit number = port number, Data when output, Weak pull-up when input
0xB3
PORTGC
Bit number = port number, Input or output setting of port
0xB4
PORTGP
Bit number = port number, Digital value at pin, Read-only
0xB5
WDSVR
Accepts the value 0x1B as a watchdog service
0xB6
T0CNTRL
WKINTEN
X
X
X
X
X
T0PND T0INTEN
0xB7
HALT
Reserved Reserved Reserved Reserved Reserved Reserved EIDLE
EHALT
0xBB
InitReg1
CLK_ADJ CMODE
unused
WDEN
BOREN
UBD
WDIS
RDIS
0xBC
InitReg2
8-bit value used internally to trim the internal oscillator frequency
0xBD
COMP
CL [5:0]
VLOOP
COUT
0xBE
XHI
X
X
X
X
X
code/data
X [9:8]
0xBF
XLO
Low 8 bits of 11-bit X register
0xCE
SP
X
X
X
X
SP [3:0]
0xCF
STATUS
EE Ready
unused
unused
Global Int.
Zero
Carry
Half Carry Negative
0xD1
InitReg3
unused
unused
BOR_TRIM [2:0]
COMP_TRIM [2:0]
0xD4 InitReg4
T1HS_DIR T1HS2_LEV T1HS1_LEV
ISOURCE_TRIM [4:0]
1. The FMS7401L’s normal mode operation begins after a system reset and is when the 8-bit microcontroller core begins executing the instruction program residing
in the code EEPROM memory.
2. The FMS7401L must be placed in a special programming mode of operation in order to have full write and read access of all of the device memories. Refer to the
In-circuit Programming Specification section of the datasheet for details.
3. Refer to the the 8-Bit Microcontroller Core section of the datasheet for additional details.
4. Refer to the Electrical Characteristics section of the datasheet.
5. The Initialization Register 2 shadow register will automatically be restored with its original factory setting during a system reset.
6. Once the read and/or write protection is enabled, the only possible external action of accessing the memory in programming mode is to issue a “Program Erase”
command through the programming interface that clears the entire code EEPROM memory contents including the volatile Initialization Register 1. This allows full
access to the user enabling new device memory programming for the single programming mode session (unless the non-volatile WDIS and RDIS bits are cleared).
Refer to the In-circuit Programming Specification section of the datasheet for addition details.
7. The register can only be read.
8. The register cannot be access during normal operation only in programming mode.
9. All SR bits except for bit 7 (the global interrupt mask) are read only when using direct, indirect, or indexed instructions. Software cannot restore SR using the tradi-
tional microcontroller methods. Refer to the 8-Bit Microcontroller Core section of the datasheet for additional details.
10.A) Names in all capital letters are predefined in the assembler. B) Names of the individual bits are not predefined and must be definced using an EQU statement
in the user program source code: for example, “APND EQU 7”. C) The initialization registers listed are the non-volatile registers. Each register has a volatile
shadow register.
REV. 1.0.3 1/24/05
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