FMS7401L_05 Datasheet, PDF (49/81 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
FMS7401L
10.1.6 Interrupt Handling
When an interrupt is recognized, the current instruction completes its execution. The return address (the current value in the
program counter, PC) is pushed onto the stack, the global interrupt (G) mask of the status register (SR) is cleared, and execu-
tion continues at the address specified by the respective interrupt vector (see Table 30). This process takes five instruction
cycles to complete. The interrupt vector contains the address of the software’s interrupt service routine (ISR). Initially, the ISR
may save (if necessary) the status register’s contents. Software, however, cannot restore SR using the traditional microcontrol-
ler methods. Just before ending the ISR, software may restore the contents of SR by using only the special inherent instructions
(e.g. SC, RC and LDC) or specially defined software routines since all SR bits except for G are read only when using direct,
indirect, or indexed instructions (e.g. LD , ST, RBIT or SBIT). Upon exiting the ISR, software must clear the appropriate
triggering pending flag and execute a return-from-interrupt (RETI) instruction. The RETI instruction pulls the saved return
address off the stack in reverse order restoring PC and setting G of SR to one. Instruction execution resumes at the restored the
program counter address.
The microcontroller core is capable of supporting five interrupts. Four are maskable through G of the SR and the fifth (software
interrupt) is not inhibited by G (see Figure 17). The execution of the INTR instruction generates a software interrupt. Once the
INTR instruction is executed, the microcontroller core will interrupt whether G is set or not. The INTR interrupt is executed in
the same manner as the other maskable interrupts where PC is stacked and G is cleared. This means, if G was enabled prior to
the software interrupt the RETI instruction must be used to return from interrupt in order to restore G to one. However, if G
was not enabled prior to the software interrupt the RET instruction must be used.
In the case of simultaneous multiple interrupts, the microcontroller core prioritizes the interrupts. See Table 23 for the interrupt
service priority sequence.
Figure 17. Basic Interrupt Structure
INTR
PWM T1
T0
MIW
ADC
T1PND
T0PND
WKPND
APND
Interrupt
Pending
Flags
T1EN
T0INT
EN
WKINT
EN
AINT
EN
Interrupt Enable Bits
G
Global Interrupt
Enable
Interrupt
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