FMS7401L_05 Datasheet, PDF (28/81 Pages) Fairchild Semiconductor – Digital Power Controller

FMS7401L
PRODUCT SPECIFICATION
Table 10. Programmable Comparator Upper Voltage Reference VTHU (Levels 32 – 63)
Level
CL[5]
CL[4]
CL[3]
CL[2]
CL[1]
CL[0]
32
1
0
0
0
0
0
33
1
0
0
0
0
1
34
1
0
0
0
1
0
35
1
0
0
0
1
1
36
1
0
0
1
0
0
37
1
0
0
1
0
1
38
1
0
0
1
1
0
39
1
0
0
1
1
1
40
1
0
1
0
0
0
41
1
0
1
0
0
1
42
1
0
1
0
1
0
43
1
0
1
0
1
1
44
1
0
1
1
0
0
45
1
0
1
1
0
1
46
1
0
1
1
1
0
47
1
0
1
1
1
1
48
1
1
0
0
0
0
49
1
1
0
0
0
1
50
1
1
0
0
1
0
51
1
1
0
0
1
1
52
1
1
0
1
0
0
53
1
1
0
1
0
1
54
1
1
0
1
1
0
55
1
1
0
1
1
1
56
1
1
1
0
0
0
57
1
1
1
0
0
1
58
1
1
1
0
1
0
59
1
1
1
0
1
1
60
1
1
1
1
0
0
61
1
1
1
1
0
1
62
1
1
1
1
1
0
63
1
1
1
1
1
1
Voltage Reference
0.46V
0.51V
0.56V
0.61V
0.66V
0.71V
0.76V
0.81V
0.86V
0.91V
0.96V
1.01V
1.06V
1.11V
1.16V
1.21V
1.27V
1.32V
1.37V
1.43V
1.48V
1.53V
1.58V
1.63V
1.68V
1.73V
1.78V
1.83V
1.88V
1.94V
1.99V
2.04V
5.2 Hardware Voltage and Current Loop Control (VLOOP=1)
The Programmable Comparator circuit is configured to compare the G4/AIN0 or G2/AIN2 non-inverting input against the out-
put of the Uncommitted (Error) Amplifier (AOUT) when configured in a voltage/current loop control mode. In the voltage/cur-
rent loop control, the inner (current) loop is performed by comparing the level on the G4/AIN0 or G2/AIN2 input against the
voltage present at the Uncommitted (Error) Amplifier (AOUT). The Uncommitted Amplifier performs the outer (voltage) loop
control by detecting the error signal and driving the current control loop to modify the PWM duty cycle (see Figure 9). The
FMS7401L voltage/current loop configuration can be used in SMPS applications where the digital loop control does not have
the required accuracy and speed. Refer to the ADC Circuit section of the datasheet for the Uncommitted Amplifier configura-
tion details.
When VLOOP=1, the comparator output (COUT) is 1 when the G4/AIN0 or G2/AIN2 input pin rises above AOUT. As long as the
input stays above AOUT, the COUT signal will hold its state. The COUT signal will equal zero if the G4/AIN0 or G2/AIN2 input
voltage falls below AOUT or if the Programmable Comparator circuit is disabled. If the digital delay filter circuit is enabled
(EPWM=0), the COUT signal is monitored for its rising edge to generate the PWMOFF signal. Refer to Figure 9 and the
following Digital Delay Filter with PWMOFF Output section for addition details.
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REV. 1.0.3 1/24/05