FMS7401L_05 Datasheet, PDF (12/81 Pages) Fairchild Semiconductor – Digital Power Controller

FMS7401L
Divide
by 2
A N 1 G / I 3
F_RCLK1
Figure 4. External Clock Scheme
PRODUCT SPECIFICATION
FMODE
REFBY2
A
B ^Sel
Y
F_RCLK2
(F_PLL)
F_(FS=0)
A
C Digital lock
F_PWMCLK
PLLEN
Multiplier
(PLL)
Y
B _Sel
FS[1]
FS[0]
FSEL
A ^Sel
Y
B
F_ICLK
F_T1CLK
1. Refer to the Device Memory section of the datasheet for details regarding the Initialization Registers 1.
2. The upper FOSC frequency (4MHz) is not a standard feature offered on the FMS7401L devices but is available upon request.
3. The ADCNTRL2 register is defined in the ADC Circuit section of the datasheet.
4. The PSCALE register is defined in the PWM Timer 1 Circuit section of the datasheet.
5. Software must always configure the device’s entire clocking structure (see Figure 3 and Figure 4) while the PWM Timer 1 circuit is off (T1C0=0) and configured in
PWM mode (T1C3=0).
6. The PLL’s F(FS=0) output is not affected by the FS[1:0] bit value of the PSCALE register and merely shares the FS[1:0]=00 divide factor.
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REV. 1.0.3 1/24/05