FMS7401L_05 Datasheet, PDF (13/81 Pages) Fairchild Semiconductor – Digital Power Controller

PRODUCT SPECIFICATION
FMS7401L
3 Power Saving Modes
The FMS7401L has both Halt and Idle power saving modes. Each mode is controlled by software and offers the advantage of
reducing the total current consumption of the device in an application. For all current consumption details, please refer to the
Electrical Characteristics section of the datasheet.
3.1 Halt Mode
Halt Mode is a power saving feature that almost completely shuts down the device for current conservation. The device is
placed into Halt Mode by setting the Halt enable bit (EHALT) of the HALT register using either the “LD M, #” or the “SBIT #,
M” instructions in the software. EHALT is a write only bit and is automatically cleared upon exiting Halt Mode. When enter-
ing Halt Mode, the internal oscillator and all other on-chip systems including the Programmable Comparator (COMP) and
Brown-out Reset (BOR) circuits are shut down.
The device can exit Halt Mode only by the Multi-input Wakeup (MIW) circuit.¹ Therefore, prior to entering Halt Mode, soft-
ware must first configure the MIW circuit. After a wakeup from Halt Mode, a THALT_REC2 start-up delay is initiated to allow the
internal oscillator and other analog circuits to stabilize before normal device execution resumes. Immediately after exiting Halt
Mode, software must clear the Power Mode Clear (PMC) register by using only the “LD M, #” instruction (see Figure 5).
Table 4. HALT Register Definition
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
HALT Register (addr. 0xB7)
Bit 4
Bit 3
Reserved
Reserved
Bit 2
Reserved
Bit 1
EIDLE
Bit 0
EHALT
Figure 5. Recommended Halt/Idle Flow
Normal Mode
Normal Mode
Multi-Input
Wakeup
LD HALT, #01H
Halt Mode
LD PMC, #00H
Resume Normal
Mode
Timer 0
Overflow
Multi-Input
Wakeup
LD HALT, #02H
Idle Mode
LD PMC, #00H
Resume Normal
Mode
3.1.1 PLL Steps for Halt Mode
When using Halt Mode and the PLL in an application, software must take the appropriate steps in order to keep the integrity of
the clock structure before entering and after exiting Halt since the PLL must be disabled. While in Halt Mode, all other device
circuits except for the MIW are disabled. Once the PLL is disabled, all output frequencies are turned off. If the PLL is re-
REV. 1.0.3 1/24/05
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