FMS7401L_05 Datasheet, PDF (26/81 Pages) Fairchild Semiconductor – Digital Power Controller

FMS7401L
PRODUCT SPECIFICATION
Bits 7-2 (CL[5:0]) is the comparator voltage threshold level selection bits of the Comparator Control (COMP) register. The CL
bits may be programmed to select one of the voltage threshold levels as the inverting input of the analog comparator. Refer to
Table 9 and Table 10 for a detailed list of voltages.
Bit 1 of the Comparator Control (COMP) register is the Programmable Comparator circuit’s voltage loop (VLOOP) configura-
tion enable bit. If VLOOP=0, the Programmable Comparator circuit is configured to compare the analog G4/AIN0 or G2/AIN2
input (COMPSEL=0 or 1) to one of the 63 voltage threshold levels. If VLOOP=1, enables the voltage loop configuration where
the analog G4/AIN0 or G2/AIN2 input (COMPSEL=0 or 1) to the Uncommitted (Error) Amplifier output (AOUT).
Bit 7 of the Digital Delay (DDELAY) register is the Programmable Comparator circuit enable (COMPEN) bit. If COMPEN=0,
the Programmable Comparator circuit is disabled and the COUT signal is low. If COMPEN=1, the Programmable Comparator
circuit is enabled and the COUT signal generated by the comparison of the two inputs.
The comparator output (COUT) signal is latched by the main system instruction (FICLK) clock into bit 0 (COUT) of the Compar-
ator Control (COMP) register. Software may only read the COUT bit to monitor the comparator’s activity. The COUT bit
cannot cause a microcontroller hardware interrupt or perform any other action.
Figure 8. Programmable Comparator Block Diagram (VLOOP = 0)
A 2 2 G / IN
COMPSEL
ADCNTRL2[6]
DDELAY
Register
EPWM DD[3] DD[2] DD[1] DD[0]
5
3210
A 0 G4/ IN
ACH5
Adjust Reference Voltage
F_RCLK2
En _{DIGITAL DELAY}
CIRCUIT
Comparator
+
_
PWMOFF (WKEN[6])
COUT
7
CL[5]
6
CL[4]
5
CL[3]
4
CL[2]
3
CL[1]
2
CL[0]
1
VLOOP
0
COUT
Comparator tr Con ol
O P (C M ) Register
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REV. 1.0.3 1/24/05