FMS7401L_05 Datasheet, PDF (10/81 Pages) Fairchild Semiconductor – Digital Power Controller

FMS7401L
PRODUCT SPECIFICATION
2 Clock Circuit
The FMS7401L may be clocked using its internal oscillator circuit or using an external digital clock signal. The desired clock
source is selectable by the CMODE bit of the Initialization Register 1.¹ During the reset sequence, the CMODE bit is updated
and the desired clock source (also called the device reference clock or FRCLK1) takes control of the device. All devices are
defaulted from the factory to use the internal oscillator as their main system instruction clock source. After power-up, the inter-
nal oscillator runs continuously unless entering Halt Mode or using an external clock source.
Table 2. CMODE Bit Definition
CMODE
0
1
FRCLK1 Clock Source
Internal Oscillator (@ FOSC)
External digital clock (G1/AIN3)
The internal oscillator signal is factory trimmed to yield the FOSC frequency as specified in the Electrical Characteristics section
of the datasheet. If the external digital clock is selected, the input signal must have a 50/50 duty cycle, can range from DC to
the FOSC, and must be available upon power-up. When the device is driven using an external clock source, the clock input to the
device should be provided through the AIN3/G1 input.
Once the source of FRCLK1 is selected, the clock is then used as the reference clock for the PLL, the clock to the digital filter in
the Programmable Comparator circuit, and is divided-by-2 to be used as the main system instruction clock (FICLK) of the device
(see Figure 3 and Figure 4).
2.1 PLL
The FMS7401L has an internal digital clock multiplier (PLL) that steps-up the FRCLK1 frequency by a multiplication factor of
32. The multiplied PLL output is then divided by a factor of 1, 2, 4, and 8 in order to generate its programmable output fre-
quencies that may be used as the main system instruction clock or by the PWM Timer 1 circuit. The PLL provides the ability to
run the PWM Timer 1 circuit at a frequency as high as 64MHz while the rest of the device operates at a much slower frequency
keeping the total current consumption low.
The reference clock of the PLL is defined by the FRCLK2 signal (as shown in Figure 3 and Figure 4) and sourced by the FRCLK1
signal. In order to yield the proper output frequencies offered by the PLL, FRCLK2 must operate at the FPLL frequency as speci-
fied in the Electrical Characteristics section of the datasheet. In the case that FRCLK1 is operating at the upper FOSC frequency,²
the REFBY2 bit in the ADCNTRL2 register³ must be set in order to divide the FRCLK1 by 2 to yield the appropriate FPLL fre-
quency of the FRCLK2 signal. Once the REFBY2 bit is set, the FRCLK2 signal that drives the PLL and digital filter in the Pro-
grammable Comparator circuit operates at a FRCLK1/2 frequency. If an external digital clock is sourcing FRCLK1, the input signal
must be supplied at the specified FOSC frequency in order to meet the specified FPLL frequency of the FRCLK2 signal.
Table 3. PLL Frequency Selection (FPLL/FOSC = 2MHz)
FS[1:0]
FRCLK2
FICLK
(FMODE = 0)
0
0
2 MHz
1 MHz
0
1
2 MHz
1 MHz
1
0
2 MHz
1 MHz
1
1
2 MHz
1 MHz
FICLK
(FMODE = 1)
8 MHz
8 MHz
8 MHz
8 MHz
FPWMCLK
8 MHz
16 MHz
32 MHz
64 MHz
The PLL outputs may be used to clock both the PWM Timer 1 circuit and the main system clock. However, the PLL must first
be enabled by setting the PLLEN bit of the PSCALE register.⁴ Once set, the PLL is turned on and begins the locking phase.
Before using any of the PLL outputs, software must wait the TPLL_LOCK to ensure that the PLL is locked into its appropriate fre-
quency and in phase. The PLLEN bit may not be changed while the PWM Timer 1 circuit is in run mode.⁵ Any write attempts
to this bit during this condition will not change its value.
The PWM Timer 1 circuit may be clocked either by the PLL’s FPWMCLK output or by the main system clock (FICLK). The FSEL
bit of the PSCALE register⁴ selects between the PLL’s FPWMCLK output (if FSEL=1) or FICLK (if FSEL=0). The FSEL bit may
not be set if the PLL is not enabled (PLLEN=0) or changed while the PWM Timer 1 circuit is in run mode.⁵ Any write attempts
to this bit during these conditions will not change its value.
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REV. 1.0.3 1/24/05