FMS7401L_05 Datasheet, PDF (55/81 Pages) Fairchild Semiconductor – Digital Power Controller

FMS7401L
PRODUCT SPECIFICATION
prior to leaving the factory with the appropriate calibration value and with the ports configured as tri-state inputs. In program-
ming mode, the default port configuration may be changed; however, be sure to maintain the factory current source calibration
value since writes to a single register must affect all bits.
The Initialization Registers 1, 2, 3 and 4 can be read from and written to while in programming mode. However, re-trimming
the internal oscillator and re-calibrating the analog circuits once the device has left the factory is discouraged and will void all
device guarantees.
Table 26. Initialization Register 1 Bit Definitions
Bit 7
CLK_ADJ
Bit 6
CMODE
Initialization Register 1 (volatile/non-volatile addr. 0xB9, 0xBB)
Bit 5
Bit 4
Bit 3
Bit 2
unused
WDEN
BOREN
UBD
Bit 1
WDIS⁶
Bit 0
RDIS⁶
(7)
CLKADJ
When set, the internal clock trimming register (volatile Initialization Register 2, Addr. 0xBA) can be
accessed by the core in order to modify the internal clock frequency.
(6)
CMODE
Clock mode select: 0 = Internal Oscillator, 1 = External Oscillator
(4)
WDEN
If set, the on-chip processor Watchdog Timer resets are enabled.
(3)
BOREN
If set, the on-chip Brown-out Reset comparator circuit is enabled.
(2)
UBD
If set, write access of the upper 32 bytes of the data EEPROM (0x60-0x7F) is disabled in both
programming and normal mode.^1,2
(1)
WDIS⁶
If set, write access of the device memory is permanently disabled while in programming mode.²
(0)
RDIS⁶
If set, read access of the device memory is permanently disabled while in programming mode.²
Table 27. Initialization Register 3 Bit Definitions
Initialization Register 3 (volatile/non-volatile addr. 0xD0, 0xD1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
unused
unused
BOR_TRIM
Bit 2
Bit 1
COMP_TRIM
Bit 0
(5:3)
(2:0)
BOR_TRIM
COMP_TRIM
These three bits allow for the calibration of the Brown-out Reset comparator circuit.
These three bits allow for the calibration of the Programmable Comparator’s upper range circuit.
Table 28. Initialization Register 4 Bit Definitions
Initialization Register 4 (volatile/non-volatile addr. 0xD3, 0xD4)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1HS_DIR
T1HS2_LEV T1HS1_LEV
ISOURCE_TRIM[4:0]
(7)
(6:5)
(4:0)
T1HS_DIR
T1HSx_LEV
ISOURCE_TRIM
Initializes during reset, the T1HS1 (G0) and T1HS2 (G5) I/O ports both either inputs or outputs.
This bit shadows directly to bits 0 and 5 of PORTGC.
Initializes during reset, the individual T1HS1 (G0) and T1HS2 (G5) I/O port level. These bits
shadow directly to bits 0 and 5 of PORTGD.
These five bits allow for the calibration of internal current source generator.
55
REV. 1.0.3 1/24/05