FMS7401L_05 Datasheet, PDF(20/81 Page) Fairchild Semiconductor

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FMS7401L_05 Datasheet, PDF (20/81 Pages) Fairchild Semiconductor – Digital Power Controller

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FMS7401L

PRODUCT SPECIFICATION

options must be prepared prior to setting the ENDAS bit. Refer to the following ADC Gated Auto-sampling Mode section for

additional details. The ADSTROBE signal is generated by the PWM Timer 1 circuit and is conï¬gured using its T1CMPB and

T1RA registers. Refer to the PWM Timer 1 Circuit section of the datasheet for details regarding its operation. If ENDAS=0,

the ADC circuit is conï¬gured to accept only ADC start commands issued by software when setting the ASTART bit of the

ADCNTRL1 register to 1. Refer to the following ADC Conversion Modes section for additional details.

Bits 3 and 2 (ASPEED[1:0]) of the ADCNTRL2 register selects the divide factor (1, 2, 4, or 8) to slow the FADCLK clock

extending the ADC conversion cycle time. In most cases, the FADCLK clock division is performed to improve the ADC

conversion accuracy. Refer to the following ADC Conversion Clock Conï¬guration section for addition details.

Bit 1 of the ADCNTRL2 register is the Current Source Generator Enable (ENIS) bit. If ENIS=0, the Current Source Generator

circuit is disabled and its G3/AIN1 pin may be used as a normal I/O port or as a standard ADC conversion input through the

analog ACH2 channel. If ENIS=1, the Current Source Generator circuit is enabled and its pin connection must be conï¬gured as

a tri-state input bypassing the I/O circuitry.9 If the ADC circuit is performing a conversion on the analog ACH2 input when

driven by the Current Source Generator, software must avoid clearing the ENIS bit. Refer to the following Current Source

Generator section for additional details.

Bit 0 (GAIN) of the ADCNTRL2 register is the autozero ampliï¬er enable bit. If GAIN=0, the autozero ampliï¬er with its gain

16 circuitry is disabled where its G4/AIN0 pin connections may be used as a normal I/O port. The G4/AIN0 pin may still be

used as a standard ADC conversion input through the analog ACH1 channel. If GAIN =1, the autozero ampliï¬er with its gain

16 circuitry is enabled and its G4/AIN0 pin connection must be conï¬gured as a tri-state input where G4/AIN0 is the non-

inverting and SR_GND is the inverting input of the ampliï¬er.9 Software may write to the GAIN bit at any time; however, the

actual GAIN enable signal will not change while an ADC conversion is in progress. If a read command is issued while a con-

version is in progress, the current value of the GAIN bit may not necessarily reï¬ect the actual state of the GAIN enable signal.

The last value of the GAIN bit written by software at the time of the ADC conversion trigger, dictates the state of the GAIN

enable signal for the triggered ADC conversion cycle. Refer to the following Autozero Ampliï¬er section for additional details.

REV. 1.0.3 1/24/05

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