FIN1215MTDX Datasheet, PDF (9/20 Pages) Fairchild Semiconductor – LVDS 21-Bit Serializers / De-Serializers

Transmitter AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Transmitter Output Data Jitter (f=85 MHz, FIN1217 only)⁽¹²⁾
Min. Typ. Max. Units
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
Figure 20
a= ¹
f ×7
f=40MHz
-0.2
0
0.2
ns
a-0.2
a
a+0.2
ns
2a-0.2
2a
2a+0.2
ns
3a-0.2
3a
3a+0.2
ns
4a-0.2
4a
4a+0.2
ns
5a-0.2
5a
5a+0.2
ns
6a-0.2
6a
6a+0.2
ns
350
370
tJCC
Transmitter Clock Out Jitter, Cycle-to cycle f=65MHz
Figure 23
f=85MHz
FIN1217 only
210
230
ps
110
150
tTPLLS
Transmitter Phase Lock Loop Set Time⁽¹³⁾ Figure 15⁽¹²⁾
10.0
ms
Notes:
11. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle
10ms after VCC reaches 3V and /PwrDn pin is above 1.5V.
12. This output data pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit
mapping difference (see Figure 19). Figure 20 shows the skew between the first data bit and clock output. A
two-bit cycle delay is guaranteed when the MSB is output from transmitter.
13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter
of less than 2ns.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
9
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