FIN1215MTDX Datasheet, PDF (14/20 Pages) Fairchild Semiconductor – LVDS 21-Bit Serializers / De-Serializers

AC Loadings and Waveforms
Note: The worst-case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O.
Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or failing edge data strobe.
Figure 7. Worst-Case Test Pattern
Figure 8. Transmitter LVDS Output Load and Transition Times
Figure 9. Receiver LVTTL/CMOS Output Load and Transition Times
Figure 10. Transmitter Set-up/Hold and HIGH/LOW Times (Rising Edge Strobe)
Figure 11. Transmitter Input Clock Transition Time
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
14
www.fairchildsemi.com