FIN1215MTDX Datasheet, PDF (4/20 Pages) Fairchild Semiconductor – LVDS 21-Bit Serializers / De-Serializers

Receivers
Pin Configuration
Figure 4. FIN1216 / FIN1218 (3:21 Receiver)
Pin Definitions
Pin Names
RxIn
RxIn+
RxCLKIn-
RxCLKIn+
RxOut-
RxCLKOut
/PwrDn
PLL VCC
PLL GND
LVDS VCC
LVDS GND
VCC
GND
NC
I/O
Type
I
I
I
I
O
O
I
I
I
I
I
I
I
# of
Pins
3
3
1
1
21
1
1
1
2
1
3
4
5
Description of Signals
Negative LVDS Differential Data Output
Positive LVDS Differential Data Output
Negative LVDS Differential Clock Output
Positive LVDS Differential Clock Output
LVTTL Level Data Outputs Goes HIGH for /PwrDn LOW
LVTTL Level Clock Output
LVTTL Level Input; Refer to Transmitter and Receiver Power-up and Power-down
Operation Truth Table
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pins for LVDS Inputs
Ground Pin for LVDS Inputs
Power Supply Pins for LVTTL Outputs
Ground Pins for LVTTL Outputs
No Connect
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
4
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