FIN1215MTDX Datasheet, PDF (16/20 Pages) Fairchild Semiconductor – LVDS 21-Bit Serializers / De-Serializers

AC Loadings and Waveforms (Continued)
Figure 16. Receiver Phase Lock Loop Set Time
Figure 17. Transmitter Power-down Delay
Figure 18. Receiver Power-down Delay
Note: This output date pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit
mapping difference. Two-bit cycle delay is guaranteed with the MSB is output from transmitter.
Figure 19. Parallel LVTTL Inputs Mapped to Three Serial LVDS Outputs
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
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