FIN1215MTDX Datasheet, PDF (12/20 Pages) Fairchild Semiconductor – LVDS 21-Bit Serializers / De-Serializers

Receiver AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min. Typ. Max. Units
tRSPB0
tRSPB1
tRSPB2
tRSPB3
tRSPB4
tRSPB5
tRSPB6
tRSPB0
tRSPB1
tRSPB2
tRSPB3
tRSPB4
tRSPB5
tRSPB6
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit 2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit 2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
Figure 21
f=65MHz
Figure 21
f=85MHz
FIN1218 only
f=40MHz, Figure 22
0.7
2.9
5.1
7.3
9.5
11.7
13.9
0.49
2.17
3.85
5.53
7.21
8.89
10.57
490
1.4
ns
3.6
ns
5.8
ns
8.0
ns
10.2 ns
12.4 ns
14.6 ns
1.19 ns
2.87 ns
4.55 ns
6.23 ns
7.91 ns
9.59 ns
11.27 ns
ps
tRSKM
RxIn Skew Margin^{(Error! Reference source not f=65MHz, Figure 22}
400
found.)
f=85MHz
FIN1218 only
252
Figure 22
tRPLLS
Receiver Phase Lock Loop Set Time Figure 16
10.0 ms
Notes:
16. Total channel latency from serializer to deserializer is (T + tTCCD) + (2•T + tRCCD).
17. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and
minimum/maximum bit position.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
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